DescriptionWith the introduction of the RISC-V instruction set architecture (ISA) and its rapidly growing ecosystem and community, there may be a unique opportunity to broaden participation in computer architecture design to groups who have been traditionally severely underrepresented. The RISC-V being an open, royalty-free ISA with many extension specifications, offers a high degree of customization and represents an attractive option for many applications, ranging from machine learning accelerators to secure computer systems design. We will present the Trireme toolbox - a RISC-V based architecture design exploration suite for education and research. Trireme comprises different processor architectures, a graphical user interface (GUI) tool to automate fast complete system generations, and a RISC-V assembly simulator. During the session, we will (1) introduce the Trireme tool, (2) show its functionalities, and (3) run hands-on design exploration examples with the attendees. Included with the Trireme Tool suite are (i) different complexity RISC-V cores (e.g., single-cycle core, multiple-cycle, and reconfigurable pipelined), (ii) a programmable memory system with reconfigurable multi-level cache subsystems, (iii) a parameterized interconnect network, (iv) Trireme explorer GUI for automatic synthesizable Verilog core and multicore system generation, and (iv) the Trireme simulator for software RISC-V instruction emulation. Trireme is an in-browser tool; therefore, it requires no installation and avoids all OS dependencies for an easy, fast, and intuitive use of the tool. It allows students and researchers to experiment with the RISC-V ISA features and quickly bring up complete and fully working architectures.